One Week ATAL FDP on Recent Trends in AI/ML/DL Hardware Acceleration: FPGA and ASIC Design for High-Performance and Energy Efficient Computing

Organizer: Department of Electronics & Communication Engineering,
Saranathan College of Engineering, Trichy

About the FDP

  • When: 04.12.2023 to 09.12.2023
  • Time: 04th December 2023 to 09th December 2023
  • MODE: Offline (Physical mode)
  • Free Registration
  • Number of participants is limited to 50

The Program will be conducted through
offline mode. Minimum 80% attendance and 60% marks is to be obtained in Assessment test conducted during program to obtain the Certificate

Resource persons are from reputed institutions and hands on session with Entuple Technologies pvt. Ltd., Bangalore

ABOUT THE PROGRAM

The Faculty Development Program (FDP) is intended to provide opportunity for faculty
members from professional institutions and research scholars to enrich their knowledge in the area of Hardware accelerators required for AI/ML/DL Hands-on training and Application Development using CADENCE and Xilinx will be given by eminent professors from Industry and Academicians from NIT and from reputed institutions.

PROGRAMME CONTENT

  • Foundations of AI/ML/DL and Hardware acceleration.
  • Hardware Acceleration landscapes for AI/ML/DL:CPU, GPU, FPGA and ASIC.
  • Understanding FPGA and its suitability for Hardware Acceleration.
  • FPGA Programming Paradigms.
  • Energy Efficient Deep Neural Network.
  • ASIC design flow and Power and performance optimization in ASIC design.
  • ML & Al Applications in automated integrated circuit design and optimization.
  • Advanced topics and future trends.
  • Research issues and case studies.

Register Here

WHO CAN ATTEND

The faculty members of AICTE approved institutions, research scholars, PG Scholars, participants from Government, MoE/AICTE/UGC, bureaucrats/ technicians/participants from industry.

SELECTION CRITERIA

The number of participants is limited to 50. Selection of the participants will be based on the first come first serve basis.
Accommodation will be provided within the college campus on request @ Rs. 200+18% GST per day

RESOURCE PERSONS

Dr.G.Lakshminarayanan, Professor National Institute of Technology. Trichy

Dr.Varun. P Gopi, Asst. Professor National Institute of Technology, Trichy.

Dr.K.Swaminathan, Principal Engineer, SmartIOPS.Trivandrum.

Mr. B.K. Shivaprasad, Execution Manager Entuple Technologies Pvt. Ltd.

Dr.J.Manikandan, Professor PES University, Bangalore.

Dr.S.Kumaravel, Assoc. Professor VIT, Vellore.

Dr.M.Santhi, Professor & Head Saranathan College of Engineering, Trichy.

Dr.C.Vennila, Professor, Saranathan College of Engineering. Trichy.

Dr.M.Padmaa, Professor Saranathan College of Engineering. Trichy.

Dr.S.A.Arunmozhi, Assoc. Professor Saranathan College of Engineering, Trichy.

Dr.V.Mohan, Assoc. Professor Saranathan College of Engineering, Trichy.

ORGANIZING COMMITTEE

PATRON

Shri. S.RAVINDRAN, Secretary PRESIDENT

Dr. D.VALAVAN, Principal COORDINATOR

Dr. M.SANTHI, Ph.D., Professor & Head,ECE CO-COORDINATOR

Dr. C.VENNILA, Ph.D., Professor, ECE & Faculty Members of ECE Department

COORDINATOR

Dr. M.SANTHI, Ph.D., Professor & Head, ECE, Saranathan College of Engineering

CO-COORDINATOR

Dr.C.VENNILA, Ph.D., Professor, ECE, Saranathan College of Engineering

ADDRESS FOR CORRESPONDENCE

Dr.M.Santhi, Professor & Head
Dr.C.Vennila. Professor, Department of ECE, Saranathan College of Engineering.
Tiruchirappalli-620012. Tamil Nadu.

E-mail: saracce2023@gmail.com
Phone: 9894047396/8122547790

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